Location: Bangalore, India
Work Arrangement: Onsite

Role Overview

As a Staff Custom Layout Engineer at Velaura AI, you will develop high-quality custom layouts for advanced digital and mixed-signal circuits targeting next-generation semiconductor technologies. Working closely with circuit design, physical design, reliability, and methodology teams, you will optimize layouts for performance, power, area (PPA), manufacturability, and reliability while contributing to the successful delivery of advanced silicon products.

Responsibilities

• Develop custom layouts for digital circuits using Cadence Virtuoso for advanced process technologies, including FinFET and Gate-All-Around (GAA).
• Optimize layouts to achieve best-in-class Power, Performance, and Area (PPA) while ensuring manufacturability and design robustness.
• Perform physical verification using industry-standard DRC, LVS, and ERC verification tools.
• Execute parasitic extraction using StarRC or Quantus and support post-layout circuit validation.
• Perform reliability verification, including electromigration (EM), IR-drop, and related sign-off analyses.
• Collaborate with circuit design teams to optimize layouts for Layout Dependent Effects (LDE), matching, routing, and device performance.
• Contribute to layout methodology improvements, design automation, and continuous process enhancements.

Required Qualifications

• Strong experience in custom layout development for advanced CMOS technologies.
• Hands-on experience with FinFET and/or Gate-All-Around (GAA) process technologies.
• Good understanding of Layout Dependent Effects (LDE) and their impact on circuit performance.
• Experience with Cadence Virtuoso Layout Suite and industry-standard physical verification tools.
• Familiarity with parasitic extraction using StarRC or Quantus.
• Exposure to EM/IR analysis and reliability verification methodologies.
• Experience collaborating with circuit design and physical design teams throughout the design cycle.

Preferred Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• Strong understanding of CMOS fabrication, MOSFET operation, RC effects, and semiconductor device physics.
• Experience with EDA tools such as Cadence Virtuoso, Calibre, Pegasus, or Synopsys ICV for layout and physical verification.
• Understanding of digital circuit design, standard cell architecture, and SRAM layouts.
• Basic knowledge of ASIC implementation and sign-off flows.
• Programming or automation experience using Python, Tcl, or Perl.
• Understanding of ESD protection, latch-up prevention, and reliability-aware layout practices.
• Exposure to post-layout simulation and timing validation.
• Experience contributing to layout automation and methodology development.
• Experience mentoring junior engineers and driving layout best practices.
• Excellent communication, analytical, and problem-solving skills, with a strong sense of ownership and the ability to deliver under aggressive tapeout schedules.
• Background in custom layout design for advanced semiconductor technologies; digital and mixed-signal layout implementation; physical verification (DRC, LVS, ERC) and parasitic extraction; reliability verification including EM/IR analysis; advanced-node design methodologies including FinFET and GAA; or cross-functional collaboration with Circuit Design, Physical Design, and Verification teams.

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company’s long-term success.

The base pay range for this role is between $125k to $275k, and your base pay will depend on your skills, qualifications, experience, and location
In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms.
If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity.
Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: careers@velaura.ai. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.