For an exciting well-funded start-up, we are looking for layout engineers.

You will develop high end ADC/DAC in an advanced process for optical communication.

Requirements:

Minimum Qualifications

Experience of 10+ years in sub micro process (2n up to 16n TSMC)

This experience must include:

• Expertise in technical leading high speed low noise layout design
• Expertise in Cadence Layout tools
• TSMC FIN FET and/or Gate All Around technologies design
• Good understanding of schematic flow
• Teamwork
• Experience in tape-out procedures
  
  

Preferred Qualifications

• Highly motivated
• Learning abilities
• Good communication
• Experience in both Mentor and Cadence tools is an advantage